1. Field of the Invention
The present invention relates to the field of computer architecture. More specifically, the present invention relates to branch prediction storage.
2. Description of the Related Art
Speculative multi-issue processors utilize branch prediction to keep pipelines full despite control hazards and to improve performance. Conventional branch prediction techniques aim to be highly accurate because the benefit provided by a branch prediction technique relates to its accuracy, cost of mispredictions, and frequency of branch instruction instances in code. The cost of mispredictions is the considerable number of cycles wasted on executing the wrong instruction instance and on restoring the processor state.
The trend in branch prediction techniques is to increase both the amount of work performed by processors and the amount of information maintained by processors. As a result, modern branch prediction techniques and implementations tend to increase the area of processors consumed by a branch predictor for logic and storage of history and/or prediction information. Although branch prediction can provide substantial performance improvements, increases in the amount of circuitry and logic area consumed by branch prediction storage can be significant and costly.
Accordingly, techniques are desired whereby branch prediction performance improvements can be achieved with less dramatic increases in layout area and storage.